0 to 16V, Hot-Swap Controller with 10-Bit
Current, Voltage Monitor, and 4 LED Drivers
16
duration t
SU
. Refer to the thermal resistance charts in
the MOSFET data sheet to determine the junction tem-
perature rise during startup, and ensure that this does
not exceed the maximum junction temperature for worst-
case ambient conditions.
Circuit-Breaker Protection
As the channel is turned on and during normal operation,
two analog comparators are used to detect an overcur-
rent condition by sensing the voltage across an external
resistor connected between SENSE and MON. If the volt-
age across the sense resistor is less than the slow-trip
and fast-trip circuit-breaker thresholds, the GATE output
remains high. If either of the thresholds is exceeded due
to an overcurrent condition, the gate of the MOSFET
is pulled down to MON by an internal 500mA current
source.
The higher of the two comparator thresholds, the fast
trip, is set by an internal 8-bit DAC (see Table 7),
within one of three configurable full-scale current-sense
ranges: 25mV, 50mV, or 100mV (see Tables 6a and 6b).
The 8-bit fast-trip threshold DAC can be programmed
from 40% to 100% of the selected full-scale current-
sense range. The slow-trip threshold follows the fast-trip
threshold as one of four programmable ratios, set by the
ifast2slow register (see Tables 4a and 4b).
The fast-trip threshold is always higher than the slow-trip
threshold, and the fast-trip comparator responds very
quickly to protect the system against sudden, severe
overcurrent events. The slower response of the slow-
trip comparator varies depending upon the amount of
overdrive beyond the slow-trip threshold. If the overdrive
is small and short lived, the comparator will not shut
down the affected channel. As the overcurrent event
increases in magnitude, the response time of the slow-
trip comparator decreases. This scheme provides good
noise rejection and spurious overcurrent transients near
the slow-trip threshold, while aggressively protecting the
system against larger overcurrent events that occur as a
result of a load fault.
Figure 1. Channel On-Off Control Logic Functional Schematic
ON
FORCE-ON
BIT
200ms DELAY,
THEN PULSE
CHANNEL
ENABLED
EN1 BIT
S
R
Q
Q
EN2 BIT
ANALOG SLOW TRIP
ANALOG FAST TRIP
UV/OV CRITICAL
PROT
S
R
Q
Q
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